1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more specifically to a power source voltage generation circuit incorporated into a semiconductor integrated circuit, a test method for this semiconductor integrated circuit, an optical and/or magnetic recording device and communication equipment having this semiconductor integrated circuit.
2. Description of the Related Art
Here, as a functional circuit using a power source voltage generation circuit incorporated into a semiconductor integrated circuit, a dynamic type memory device will be referred to in the explanation.
In a dynamic type memory device, as a method for accessing data of storage elements (memory cells) arranged in a matrix form, the operation of read and write is carried out by supplying word lines with an electric potential and exchanging the data between bit lines and the memory cells.
FIG. 11 shows a circuit configuration of a memory cell part in a general dynamic random access memory (DRAM).
In the storage operation of a DRAM, a potential of a logic “H” level or a potential of a logic “L” level sent from a bit line BL shown in FIG. 11 is used to accumulate electric charges in a memory cell capacitor CO via an access transistor TMEM so as to write data of a logic “H” level or data of a logic “L” level in the memory cell capacitor CO and to store data.
In recent years, along with the development of a DRAM to have higher integration and larger capacity, the circuit as a whole is designed to be miniaturized, and also the area of a memory cell capacitor CO tends to become more minute, so that the capacity also tends to be reduced. Here, to ensure the operation of a memory even in the case where the capacity of a memory cell capacitor CO is reduced, it is necessary to secure a charge storage time sufficiently for the memory cell capacitor CO.
For this purpose, the loss of charge from the memory cell capacitor CO, due to leakage currents via the access transistor TMEM that transmits charges, needs to be prevented.
Therefore, a measure generally taken for the DRAM to prevent the loss of charge is to apply a negative voltage to the substrate of the access transistor TMEM, thus to increase a threshold voltage VT of the access transistor TMEM, and to suppress the leakage currents via the access transistor TMEM.
FIG. 12 shows a cross-sectional structure of a memory cell transistor TMEM.
In FIG. 12, leakage components of charges from a memory cell capacitor C connected to a source (S) of an access transistor TMEM can be divided into a leakage current component I (off), directed from the source of TMEM to a drain (D), and a leakage current component I (leak), directed from a n-type impurity diffusion area of the source to a p-type substrate (p-Sub.).
Here, in FIG. 12, the current direction from the p-type area to the n-type area will be defined as a normal direction.
The graph of FIG. 13A shows the dependency of I (of) on a substrate voltage VBB, and the graph of FIG. 13B shows the dependency of I (leak) on a substrate voltage VBB.
When potential is not applied to word lines WL and the word lines are in an inactive state, it is shown in FIG. 13A that the current between the drain and a source Ids in an area indicated by (i) becomes I (off). Here, due to the application of the substrate potential VBB, the threshold voltage VT of the access transistor TMEM increases, and the inclination of the graph becomes gentle, so that the phenomenon of I (off) accompanied by the application of the substrate potential VBB is observed.
On the other hand, looking at a current Ip-n at a p-n junction shown in FIG. 13B, accompanied by the application of a negative substrate potential VBB, Ip-n increases in the third quadrant of the graph shown in FIG. 13B. This shows that, accompanied by the increase of VBB, the current from the n-type impurity diffusion area of the source to the p-type substrate is increased, that is, the leakage currents Ip-n=I (leak) from the source area to the p-type substrate of the TMEM are increased.
Next, FIG. 14 shows a general configuration of a negative voltage generation circuit, which conventionally is used for generating a negative voltage VBB to be applied to a p-type substrate.
In FIG. 14, the negative voltage generation circuit includes a substrate voltage generation part (charge pump part) 15-A and a voltage detection part 15-B. The substrate voltage generation part 15-A includes a self-oscillating circuit 15-A1, a timing generation logic circuit 15-A2 and a charge pump circuit 15-A3, and the self-oscillating circuit 15-A1 operates for a period during which a control signal BBGOE generated by the voltage detection part 15-B is in a logic “H” level.
The charge pump circuit 15-A3 is driven by a timing signal generated by the timing generation circuit 15-A2, and thus, a negative voltage VBB is generated.
This negative voltage generation circuit has the function of controlling the substrate voltage generation part 15-A by the voltage detection part 15-B and maintaining the negative voltage VBB to be applied to the substrate at a predetermined value.
FIG. 15 shows a configuration example of the voltage detection part 15-B.
In the voltage detection part 15-B shown in FIG. 15, by means of a voltage divider circuit including a P-channel transistor TP151, a N-channel transistor TN152 and resistor R153, a potential DETIN with the voltage divided from a power source voltage VDD and a substrate voltage VBB is generated, and the relative size thereof with a set voltage is judged by an inverter including P-channel transistors TP154, TP155 and a N-channel transistor TN156, which is then amplified by inverters I157, I158 and I159, and the relative size is output as a logic signal BBGOE.
FIG. 16A shows the characteristics of the negative voltage VBB relative to the power source voltage VDD in the negative voltage generation circuit shown in FIG. 14. FIG. 16B shows the characteristics of a pause time, which is a data holding time of a memory.
As shown in FIG. 16A, in the voltage detection part 15-B, as the power source voltage VDD increases, the negative voltage VBB applied to the substrate increases, whereas VBB decreases as VDD decreases. Furthermore, as shown in FIG. 16B, there is a power source voltage VDDP having the longest pause time, and when the power source voltage VDD is either larger or smaller than VDDP, the data holding time becomes shorter. This is because, when the negative voltage VBB is applied to the substrate of the memory cell transistor, as shown in FIG. 13A, the threshold voltage of the memory cell transistor increases (VT1→VT2→VT3), and the current component I (off directed from the source to the drain decreases, while the leakage current component I (leak) directed to the p-type substrate increases, due to the level change of VBB accompanied by the increase of VDD. The characteristics of the pause time shown in FIG. 16B are used to show the characteristics of a DRAM memory cell as a disturb pause (P1) caused by the decreasing current component I (off) and a static pause (P2) caused by the increasing current component I (leak).
Therefore, when the negative voltage VBB applied to the substrate is set, by taking the two kinds of leakage paths of charges mentioned above into consideration, the circuit preferably is designed in the voltage conditions for the minimum leakage charges in respective paths and also to be independent of the power source voltage. The application of such a negative voltage generation circuit can reduce the leakage currents and set a long data holding time for the memory, so that the power consumption of the memory can be reduced. In particular, this circuit is useful in the case where low power consumption is desired, such as for portable communication equipment and so forth.
Furthermore, when the power consumption of a circuit is reduced, heat generation can be suppressed, so that it is now possible to achieve a stable operation also for other electronic circuits.
However, the configuration of the conventional voltage detection part 15-B described above has characteristics that the potential DETIN with the voltage divided from the power source voltage VDD and the substrate potential VBB is used for judging the relative size with the set voltage, so that the detected voltage changes according to the fluctuation of the power source voltage VDD.
Since an access transistor TMEM connected to a memory cell capacitor CO has different characteristics depending on whether the power source voltage VDD is low or high, there was a problem that the characteristics of the memory cannot be exhibited sufficiently according to the conditions of the power source voltage VDD.
Furthermore, with regard to the N-channel transistor TN152 in the voltage detection part 15-B, there is a possibility that a negative voltage will be applied to its source electrode depending on the value of the substrate potential VBB, and the possibility of currents flowing from the p-substrate to the n-type impurity diffusion area of the source is conceivable.
Therefore, in order to operate the voltage divider circuit including the P-channel transistor TP151, the N-channel transistor TN152 and the resistor R153 correctly, VBB needs to be applied to the p-type substrate of the N-channel transistor TN152, and for this purpose, it is necessary to provide an area where the substrate of the N-channel transistor TN152 is separated from the surrounding substrates.
Thus, the problems arise that the production steps for manufacturing the circuit become complicated, and that the arrangement of the voltage detection part in view of the layout configuration also becomes difficult.